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SY89853U
Precision Low-Power Dual 2:1 LVPECL MUX with Internal Termination
General Description
The SY89853U features two, low jitter 2:1 differential multiplexers with 100K LVPECL (800mV) compatible outputs, capable of handling clocks up to 2.5GHz and data streams up to 2.5Gbps. The SY89853U differential inputs include Micrel's unique, 3-input termination architecture that allows users to interface to any differential signal (AC- or DCCoupled) as small as 100mV without any level shifting or termination resistors networks in the signal path. The result is a clean, stub-free, low jitter interface solution. The differential 800mV LVPECL outputs have fast rise/fall times guaranteed to be less than 180ps. The SY89853U operates from a 2.5V 5% or a 3.3V 10% supply, and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require higher performance, consider the SY58026U. The SY89853U is part of Micrel's Precision (R) Edge product family. All support documentation can be found on Micrel's web site at www.micrel.com.
Precision Edge
(R)
Features
* Dual 2:1 MUX, each channel selects from inputs * Unique, patent-pending input isolation design minimizes crosstalk * Low power 210mW (VCC = 2.5V) * Guaranteed AC performance over temperature and voltage: - DC-to->2.5Gbps data rate throughput - <360ps IN-to-Q tpd - <180ps tr/tf times * Ultra-low jitter design: - <1psRMS random jitter - <10psPP deterministic jitter - <10psPP total jitter (clock) - <0.7psRMS crosstalk-induced jitter * Unique, patent-pending 50 input termination and VT pin accepts DC- and AC-coupled inputs (CML, LVDS, PECL) * 800mV LVPECL output swing * Power supply 2.5V 5% or 3.3V 10% * -40C to +85C temperature range * Available in 32-pin (5mm x 5mm) MLF(R) package
Applications
* * * * Data communication systems All SONET OC-3 to OC-48 applications All Fibre Channel applications All GigE applications
Markets
* * * *
Precision Edge is a registered trademark of Micrel, Inc MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
LAN/WAN communication Enterprise servers ATE Test and measurement
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SY89853U
Functional Block Diagram
Truth Table
SEL 0 1 Q IN0 Input Select IN1 Input Select
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SY89853U
Ordering Information(1)
Part Number SY89853UMG SY89853UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-32 MLF-32
Operating Range Industrial Industrial
Package Marking SY89853U with Pb-Free bar-line indicator SY89853U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF(R) (MLF-32)
Pin Description
Pin Number 25, 28, 29, 32 1, 4 5, 8 Pin Name INA0, /INA0, INA1, /INA1, INB0, /INB0, INB1, /INB1 Pin Function Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50. Note that these inputs will default to an indeterminate state if left open. Connecting one input to VCC and the complementary input-to-GND through 1k resistor can terminate unused differential input pairs. The VT pin is to be left open in this configuration. Please refer to the "Input Interface Applications" section for more details. Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors. The 0.01F capacitor should be as close to VCC pin as possible. Not connected. Bank A and Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs select the inputs to the multiplexers. These inputs are internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. Differential Outputs: These LVPECL output pairs are the outputs of the device. They are a logic function of the INA0, INA1, INB0, INB1 and SELA and SELB inputs. Please refer to the "Truth Table" below for details. Input Termination Center-Tap: Each side of the differential input pair terminates to a VT pin. The VTA0, VTA1, VTB0, VTB1 pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for details. Reference Voltages: These reference voltage outputs are equivalent to VCC-1.2V. They are used for AC-coupled inputs. Connect VREF-AC directly to the VT pin and bypass with 0.01F low ESR capacitor to VCC. See "Input Interface Applications" section. Maximum sink/source current is 1.5mA. Ground: Ground pins and exposed pad must be connected to the same ground plane.
10, 13, 16, 17, 20, 23 14, 19 18 15 22, 21 12, 11 26, 30 2, 6 27 31 3 7 9, 24
VCC NC SELA, SELB QA, /QA, QB, /QB VTA0, VTA1 VTB0, VTB1 VREF-ACA0, VREF-ACA1, VREF-ACB0, VREF-ACB1 GND, Exposed Pad
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SY89853U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................-0.5V to +4.0V Input Voltage (VIN) ....................................-0.5V to VCC LVPECL Output Current (IOUT) Continuous................................................. 50mA Surge ....................................................... 100mA Termination Current Source or Sink Current on VT .................... 50mA Input Current Source or Sink Current on IN, /IN.............. 50mA Current (VREF-AC) Source or Sink Current on VREF-AC ............... 2mA Lead Temperature (soldering, 20sec.) ...............260C Storage Temperature (Ts) ................ -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) .....................+2.375V to +2.625V .....................................................+3.0V to +3.6V Ambient Temperature (TA)....................-40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air......................................................35C/W 500lfpm ....................................................28C/W MLF(R) (JB) Junction-to-Board.....................................16C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise noted.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN-to-/IN) Differential Input Voltage Swing |IN - /IN| Maximum Input Voltage (IN-to-VT) Output Reference Voltage
Condition VCC = 2.5V VCC = 3.3V No load, max. VCC.
Min 2.375 3.0 45 90 VCC- 1.2 0
Typ 2.5 3.3 65 50 100
Max 2.625 3.6 85 55 110 VCC VIH- 0.1 1700
Units V V mA V V mV mV
See Figure 1a. See Figure 1b.
100 200
1.28 VCC- 1.3 VCC- 1.2 VCC- 1.1
V V
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SY89853U
LVPECL Outputs DC Electrical Characteristics(5)
VCC = 2.5V 5% or 3.3V 10%; RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise noted.
Symbol VOH VOL VOUT VDIFF-OUT Parameter Output High Voltage (Q, /Q) Output Low Voltage (Q, /Q) Output Voltage Swing (Q, /Q) Differential Output Voltage Swing (Q, /Q) See Figure 1a. See Figure 1b. Condition Min VCC-1.145 VCC-1.945 400 800 800 1600 Typ Max VCC-0.895 VCC-1.695 Units V V mV mV
LVTTL/CMOS DC Electrical Characteristics(5)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to +85C, unless otherwise noted.
Symbol VIH VIL IIH IIL
Notes: 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
VIN = VCC VIN = 0.5V -300
75
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SY89853U
AC Electrical Characteristics(6)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated.
Symbol fMAX tpd Parameter Maximum Operating Frequency Propagation Delay IN-to-Q SEL-to-Q tpd Tempco tSKEW tJITTER Differential Propagation Delay Temperature Coefficient Input-to-Input Skew (Within-bank) Bank-to-Bank Skew Data Random Jitter (RJ) Deterministic Jitter (DJ) Clock Cycle-to-Cycle Jitter Total Jitter (TJ) Crosstalk-Induced Jitter Channel-to-Channel (Within-bank) tr, tf
Notes: 6. 7. 8. 9. High-speed AC parameters are guaranteed by design and characterization. VIN swing 100mV, unless otherwise stated. Input-to-input skew is the difference in time between two inputs to the output within a bank. Bank-to-bank skew is the difference in time from input to the output between banks. Random jitter is measured with a K28.7 character pattern, measured at 23
Condition NRZ Data Clock, VOUT > 400mV
Min 2.5 2.5 160 100
Typ
Max
Units Gbps GHz
250 260 143
360 400
ps ps fs/ C
Note 7 Note 8 Note 9 Note 10 Note 11 Note 12 Note 13, within-bank At full output swing. 50
10 12
20 25 1 10 1 10 0.7
ps ps psRMS psPP psRMS psPP psRMS ps
Output Rise/Fall Time (20% to 80%)
100
180
10. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 11. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 12. Total jitter definition: with an ideal clock input of frequency 12
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SY89853U
Typical Operating Characteristics
VCC = 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated.
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SY89853U
Functional Characteristics
VCC = 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC-2V, unless otherwise stated.
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SY89853U
Single-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagram
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SY89853U
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
Input Interface Applications
Figure 3a. LVPECL Interface (DC-Coupled)
Figure 3b. LVPECL Interface (AC-Coupled)
Figure 3c. LVDS Interface
option: may connect VT to VCC. Figure 3d. CML Interface (DC-Coupled) Figure 3e. CML Interface (AC-Coupled)
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SY89853U
Output Interface Applications
LVPECL has high input impedance, very low output (open emitter) impedance, and small signal swing, which result in low EMI. LVPECL is ideal for driving 50 and 100 controlled impedance transmission lines. There are different techniques for terminating
LVPECL outputs: Parallel Termination TheveninEquivalent, Parallel Termination (3-resistor), and ACcoupled termination. Unused output pairs may be left floating; however, single-ended outputs must be terminated or balanced.
Note: 1. For a 2.5V system, R1 = 250, R2 = 62.5 . 2. For a 3.3V system, R1 = 130, R2 = 82.
Note: 1. For a 2.5V system, Rb = 19. 2. For a 3.3V system, Rb = 50.
Figure 4a. Parallel Thevenin-Equivalent Termination
Figure 4b. Parallel Termination (3-Resistor)
Note: For a 2.5V system, R = 50.
Note: For a 2.5V system, R1 = 250, R2 = 62.5 .
Figure 4c. AC-Coupled Termination
Figure 4d. Parallel Thevenin-Equivalent Termination
Related Product and Support Documentation
Part Number SY58026U Function 5Gbps Dual 2 :1 400mV LVPECL MUX with Internal Termination MLF(R) Application Note HBW Solutions New Products and Applications Data Sheet Link www.micrel.com/product-info/products/sy58026u.shtml. www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
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SY89853U
Package Information
32-Pin MLF(R) (MLF-32)
PCB Thermal Consideration for 32-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB)
Packages Notes: 1. 2. 3. Package meets Level 2 Moisture Sensitivity Classification. All parts are dry-packed before shipment. Exposed pads must be soldered to a ground for proper thermal management.
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SY89853U
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
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